Highlights :

• Three Chip Emulation using FPGA
• Support for Xilinx Virtex, Virtex2 family or Altera APEX or other FPGA's
• Universal Daughter Board with 3 ZIF sockets
• Upgradeable with new High Density devices by changing only the adaptors and not the platform. Ensures life for the product.
• Support for SDRAM EMULATION up to 1GB
• Support for SRAM EMULATION up to 1GB and FLASH up to 1MB
• Support for 32 Bit PCI 2 SLOT adaptor: Plug any PCI static core Cards
• VHDL support for MODELSIM EE/SE
• VERILOG Support for any Simulator using PLI
• Number of I/O's per CHIP is 450.
• Number of I/O's per Board is 299.
• Several VRAP-AEB units can be cascaded
• Mix VRAP-AEB and VRAP-UCB in the same design
• VRAP-UCB can be upgraded to VRAP-AEB.
• With Suitable adaptors can be plugged on to your application board.
• Unlimited Expansion using VRAP- HUB.
• Currently available 6Million x3 : 18 Million Gate
• Adaptors comes with BGA sockets for upgrading to better chips

The ASIC design must be partitioned into ONE FPGA or TWO FPGAs or THREE FPGAs or across multiple VRAP-AEB boards. You can use any industry standard tools like Certify from Synplicity.

These boards are available from Minimum 3 Million FPGA gates to 30 Million FPGA gates per VRAP- AEB board. Each board will sit inside a VRAP-AEB unit.Each unit has board number

Who needs this products?

• Any one whose design is more than 200K gate ASIC with large memory blocks needs to prototype it on to FPGA modules
• Any one who is into processor core design or embedded design needs this type of product.
• Any one who needs to test his prototype in real speed also needs this product. With the right adaptor, the VRAP-AEB board can be fitted on your application board.
• Any one who wishs to do CO Simulation using hardware and software needs this product

SOC Design Made Easy :

Before going for silicon, we have seen that a fast prototyping of the SYSTEM is mandatory for functional validation. ASIC's normally use complex logic with huge memories in single chip. ASIC gates can be normally be multiplied by 4 to get the FPGA gates. i.e a 200K gate ASIC needs minimum 1 million gate FPGA. Usually FPGA's are FAN In limited. Any DATA PATH intensive designs need more than 4 times the standard ASIC gate count. Seldom an ASIC design can be fitted on to One Single Chip FPGA. This raises the need for partitioning the design on to multiple FPGA's. Only Designs which uses DATA PATHS, like networking, or image processing designs can easily be targeted on to multiple FPGA's

Any System On Chip design will require complex processing blocks and several memory blocks. Even functional simulation of these Systems on Software simulator will be very slow and increases the cost of testing, if one goes for regression test or 100 % test vector coverage

One solution is coupling the simulator with the MULTIPLE FPGA modules, so that the user can partition the design and download it on to several FPGA's. The testvectors are sent to the modules and results captured. This allows us to use as many modules as possible to fit the ASIC on to the FPGA's.

Case Study :

For a typical system shown below the processor, JPEG and FLASH can be fitted on to 3 Chips in ONE VRAP-AEB system and similarly another 3 modules can be fitted on to 3 chips in another VRAP-AEB system. Possibly with 3 system, one can fit all the modules.

The VRAP AEB Board (Vdesign Rapid Asic Prototyping Acceleration Emulation Board) from VDesign is used to speed up the gate level simulation by a factor of more than 1000 times faster than a software based gate level simulation. This board is also used for ASIC emulation on the customer application board.The usage of VRAP AEB runs to

• Functional Simulation Acceleration of any IP Net list
• ASIC emulation on any Customer application board

The VRAP AEB works on

• PC/Windows - 9x/NT/2000 and Workstation/Solaris
• Any VHDL/Verilog/Mixed HDL Simulator

The various specifications with which the VRAP AEB becomes so unique and special to its customers world wide could be easily understood.

In a nut shell, the VRAP AEB board, the first member of the VRAP family boards is used for VHDL/Verilog simulation acceleration at the gate level.

• Contains upto 18 million to 288 million ( Using Cascade version ) FPGA gates in 3 x FPGA
•  Maximum of 299 I/O’s
• Compilation is more than 1000 times faster
• Simulation is more than 1000 times faster
• Can mix behavioral code and VRP AEB in the same design
• Can compare between behavioral simulation and VRAP AEB

Download Application Notes: