U50K-Universal FPGA Trainer System
VRAP-UM ( University Model )
Advanced Interface Boards with U50K
DSP Cores

U50K-Universal FPGA Trainer System:

U50K FPGA trainer system is a HDL 2 FPGA system for the HDL design environment. This system is used to verify HDL code at hardware level. Debugging is simplified using an external simple membrane keypad and LCD display. The U50K board can be programmed any number of times and it comes with utility programs to download the code into the chip. The board can also be used for standard part prototyping and Small System development like microprocessor up to 50,000 gates. Most of all it has been designed and manufactured in our country. U50K system allows hardware prototyping, Which is an excellent choice for college projects. Currently projects are available for HDL environment

U50K Technical Specification:
  • Different technology support  (Altera, Atmel, Actel, Xilinx, Lucent).
    -- XILINX (SPARTAN II 50K gate density).
    -- ALTERA (ACEX1K Device 50K gate density).
  • External frequency Oscillator 16Mhz in system, up gradable up to 80Mhz to 150 Mhz.
  • Language Support (VHDL, Verilog, Mixed HDL)
  • Different Voltage support (5 Volt, 3.3 Volt, 2.5 Volt or 1.8Volt)
  • Simulator support (ModelSim)
  • Synthesis support (Leonardo Spectrum)
  • Place &Route support (XILINX Foundation and Alliance series & ALTERA MaxplusII) 
  • Prototyping board with support for 100pin QFP (optional) CPLD support, it can be linked with any DSP kit.
  • 41 external I/O s to control external devices or another FPGA suitable for Custom
  • UPLINK / DOWNLINK Possible with PC uses RS232 C (optional) 
  • It can be used to configure with BST.
  • It can be used to configure with VRAP – UM.
  • One technology can be supported at a time.
Other Adaptors:
  • MicroController / MicroProcessor
  • IC Tester
  • DSP TMS series adaptor
  • Boundary scan too

VRAP-UM ( University Model ):

VRAP-UM ( Vdesign Rapid Asic Prototype - University Model ) is an prototype board developed to speed up VHDL / Verilog simulation by a factor of 1000 or more. The VRAP-UM board includes a re-programmable chip, system software and utility programs. The board can be used for co-simulation of software and hardware, IP validation.

By using VRAP-UM the Engineer can run VHDL / Verilog RTL and structural code in the same design but the speed of the structural simulation is about 1000 times or more faster than a structural software simulation. The structural code to be fitted into VRAP-UM can contain upto 15,000 FPGA gates.

VRAP-UM Technical Specification:
  • Emulation upto 15,000 gates Xilinx-Spartan2, upgradable upto 100,000 gates*
  • Maximum of 16 I/O's, upgradable upto 40 I/O's*
  • Compilation more than 1000 times faster
  • Simulation more than 1000 times faster
  • Compare behavioral simulation result and chip level results
  • Validation of college projects on chip
  • Coupled with Model Sim SE
  • Plugged as an added advantage to U50K Trainer System
  • PCI Card Compatible
  • Supports both VHDL and VERILOG

    * Future Release

Advanced Interface Boards with U50K:

  • Analog Interface Board:

    This board produces a micro phone amplifier or programmable gain amplifier followed by programmable anti aliasing filter and 100k SP A/D converter, similarly a D/A followed by anti aliasing filter and PGA.

  • 128 KB SRAM Board

DSP Cores:

  • Digital Filter
  • FFT
  • etc
For more details on VLSI products please send your enquiries through Enquiry Form