What is RAP ? ( Rapid Asic Prototyping ) :

Today, the VLSI product developments are focused on developing compact, reliable, low power and low cost SINGLE CHIP solutions. Some of the applications include, Single chip Computer, Cell Phone, ATM processing, Digital Signal processing , Digital TV chips, etc

Currently the semiconductor industry is changing on many fronts:

• Smaller geometric features on silicon
• The reduction of internal voltage levels
• The use of complex megacells and macrocells known as cores
• The use and reuse of existing simple and complex "hard" macrocells
• The integration of huge amounts of memory
• The integration of large amounts of logic on SYSTEM-ON-A-CHIP devices.

The ability to place large volumes of logic and memory on a single die in a short period of time is expected to increase the cost of test due to longer test times and larger amounts of test vector data, and is necessary to compress the design cycle time.

So, need to prototype the system before going in for silicon and validate the complete design using extensive test vectors becomes mandatory.

RAPID ASIC PROTOTYPING makes use of re programmable FPGA chips for logic validation. The user's logic is loaded onto programmable logic and extra memory chips are added along with the logic to validate the vectors. At this point of time, the behavioural simulation is more attractive as it helps to do regression test and validate the concept.

AT the project manager level, complete functional validation is more useful and design test cycle time can be compressed by order of more than 1000 times by using cost effective Rapid Prototyping systems.

Where to we need VRAP-UCB?

FPGA Users:

Xilinx, Altera, Actel, Lucent, Lattice etc sell the complex FPGA's in millions of quantities. VDesign provides standard adaptors and standard Piggy back's for known complex FPGA components. The users of FPGA can use VRAP-UCB for physical functional validation.

Intellectual Property Vendors:

Normally IP vendors, develop a core in VHDL or VERILOG and they target the cores towards either FPGA technology or ASIC technology. They sell the VHDL or VERILOG source code and associated files for placement and routing. An extensive functional validation of the IP core is required before they can make the code ready for the market. Also they need to cater to different technologies and they need to modify the code for the particular device. They can target their IP cores towards different FPGA technology. VRAP-UCB, provides a single platform for different FPGA's from different vendors. They can download the code into the CHIP and run extensively the simulation which will save days of simulation .

IP Buyers:

But the users usually would like to evaluate the core before they buy the source code. But the IP vendors would not give the sourcecode for evaluation. Instead if the BUYERs are equipped with VRAP-UCB, the buyers can download only the FPGA CONFIGURATION file for the IP CORE. They can download the configuration file into corresponding FPGA, and connect the component and evaluate the core. Once satisfied they can place the order

EDA Synthesis Tool Developers:

Though EDA synthesis tool vendors are few in number, they do need this product to validate their synthesis technique

IC Manufacturers:

All the CMOS , STATIC core IC developers can validate their IC's against behavioural simulation and also against their previous version of the chip.

Engineering Colleges and Research Institutes:

All the pioneer Engineering Colleges and all Research Institutes can go this product. Multiprocessor , Super computer developments can plug processor cores on to the VRAP-UCB and cascade as many number as possible. Simulation now will be of the order of 10000 times much faster than the software simulator.

Defence Sector:

Defense is one industry, where the need for VRAP is absolutely justified, as even the most complex prototype can be evaluated beforehand the chip is committed for silicon.

Satellite Communication, Routers, etc:

It is in the communication and networking, where abundance data is moved in serial structure, which increases the processing time. Need for prototyping increases here.