The goal over time is to reduce the cost of manufacturing the product by reducing the per-part recurring costs:

1.Reducing the silicon cost by increasing volume and yield, and by die size reduction

2.Reducing of packaging cost by increasing volume, shifting to lower cost packages if possible ( e.g ., from ceramic to plastic), or    reduction in package pin count

3.Reduction in cost of test by

• Reducing the vector data size
• Reducing the tester sequencing complexity
• Reducing the cost of the tester
• Reducing testing time
• Simplifying the test program

What is RAP ? ( Rapid Asic Prototyping ) :

Today, the VLSI product developments are focused on developing compact, reliable, low power and low cost SINGLE CHIP solutions. Some of the applications include, Single chip Computer, Cell Phone, ATM processing, Digital Signal processing , Digital TV chips, etc

Currently the semiconductor industry is changing on many fronts:

• Smaller geometric features on silicon
• The reduction of internal voltage levels
• The use of complex megacells and macrocells known as cores
• The use and reuse of existing simple and complex "hard" macrocells
• The integration of huge amounts of memory
• The integration of large amounts of logic on SYSTEM-ON-A-CHIP devices.

The ability to place large volumes of logic and memory on a single die in a short period of time is expected to increase the cost of test due to longer test times and larger amounts of test vector data, and is necessary to compress the design cycle time.

So, need to prototype the system before going in for silicon and validate the complete design using extensive test vectors becomes mandatory.

RAPID ASIC PROTOTYPING makes use of re programmable FPGA chips for logic validation. The user's logic is loaded onto programmable logic and extra memory chips are added along with the logic to validate the vectors. At this point of time, the behavioural simulation is more attractive as it helps to do regression test and validate the concept.

AT the project manager level, complete functional validation is more useful and design test cycle time can be compressed by order of more than 1000 times by using cost effective Rapid Prototyping systems.

Electronic board designers using FPGA/ASIC

• Mother board designers using ASIC
• FPGA designers
• ASIC designers
• VLSI product developers
• IP ( Intellectual Property Developers )
• EDA synthesis tool vendor
• ASIC chip testing
• Embedded design using ARC, ARM CORE
• Memory chip testing
• Memory chip emulation
• FPGA manufacturers

ATE ( Automatic Test Equipment ) :

Integrated Circuit Automatic Test Equipment, also known as IC ATE is generally a very expensive (i.e. greater than US $1million ) test platform. The ATE can be represented as a number of channels with memory depth ( a channel basically representing the memory behind a package pin), a number of clock generators , and a number of power supplies. These resources are applied to the chip through the load board that houses the chip socket.

The ATE is not exactly the same as a simulator. A simulator can operate with or without timing, can be cycle based or event based and can access any signal, variable, or constant in a design.

The ATE on the other hand can operate only at the edge of the design through the package pins and has real signal and clock delays and signal degradations.